A Novel Architecture for 10-bit 40MSPS Low Power Pipelined ADC Using a Simultaneous Capacitor and Op-amp Sharing Technique

This work presents a low-power 10-bit 40 MSPS Pipelined ADC with 1.8V supply voltage in 180nm silicon-based CMOS process. Simultaneous capacitor sharing and op-amp technique is used between two successive stages of Sample-and-Hold Amplifier (SHA) to reduce the power consumption. The memory effect proposed eliminated by low input capacitance variable gm op-amp. differential integral nonlinearity converter within LSB. Simulation results show that required Signal-Furious-Dynamic range (SFDR) 70dB, Signal-to -Noise-plus Distortion Ratio (SNDR) 56.1dB 9.02 Effective Number Bits ( ENOB ) has been achieved 2 MHz, 1-Vp−p, diff signal while consuming only 7.3mW from supply.